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?006 fairchild semiconductor corporation 1 www.fairchildsemi.com f ebruary 2006 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs features 5v tolerant inputs and outputs 2.3v?.6v v cc speci?ations provided 8.5ns t pd max (v cc = 3.3v), 10 a i cc max po w er-down high impedance inputs and outputs supports live insertion/withdrawal 1 24ma output drive (v cc = 3.0v) implements patented noise/emi reduction circuitry latch-up performance exceeds jedec 78 conditions esd performance ?human body model > 2000v ?machine model > 200v leadless pb-free dqfn package general description the lcx374 consists of eight d-type ?p-?ps featuring separate d-type inputs for each ?p-?p and 3-state outputs for bus-oriented applications. a buffered clock (cp) and output enable (oe ) are common to all ?p- ?ps. the lcx374 is designed for low voltage appli- cations with capability of interfacing to a 5v signal environment. the lcx374 is fabricated with an advanced cmos tech- nology to achieve high speed operation while maintain- ing cmos low power dissipation. ordering information devices also available in tape and reel. specify by appending suffix letter ??to the ordering code. pb-free package per jedec j-std-020b. notes: 1. to ensure the high impedance state during power up or down, oe should be tied to v cc through a pull-up resistor: the minimum value of the resistor is determined by the current-sourcing capability of the driver. 2. dqfn package available in tape and reel only. 3. ?nl?indicates pb-free package (per jedec j-std-020b). device available in tape and reel only. order number package number package description 74lcx374wm m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74lcx374sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74lcx374bqx 2 mlp020b pb-free 20-terminal depopulated quad very-thin flat pack no leads (dqfn), jedec mo-241, 2.5 x 4.5mm 74lcx374msa msa20 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide 74lcx374mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74lcx374mtcx_nl 3 mtc20 pb-free 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide
2 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs logic symbol connection diagrams pin assignments for soic, sop, ssop, tssop p ad assignments for dqfn (top view) pin descriptions t ruth table h = high voltage level l = low voltage level x = immaterial z = high impedance = low-to-high transition o 0 = previous o 0 before high-to-low of cp functional description the lcx374 consists of eight edge-triggered ?p-?ps with individual d-type inputs and 3-state true outputs. the buffered clock and buffered output enable are com- mon to all ?p-?ps. the eight ?p-?ps will store the state of their individual d inputs that meet the setup and hold time requirements on the low-to-high clock (cp) tran- sition. with the output enable (oe ) low, the contents of the eight ?p-?ps are available at the outputs. when the oe is high, the outputs go to the high impedance state. operation of the oe input does not affect the state of the ?p-?ps. d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 o 0 oe cp o 1 o 2 o 3 o 4 o 5 o 6 o 7 d 0 d 1 o 1 o 2 d 2 d 3 o 3 gnd o 0 d 7 d 6 o 6 o 5 d 5 d 4 o 4 cp o 7 v cc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe d 0 d 1 o 1 o 2 d 2 d 3 o 3 gnd o 0 d 7 d 6 o 6 o 5 d 5 d 4 o 4 cp o 7 v cc 120 2 3 4 5 6 7 8 9 10 11 19 18 17 16 15 14 13 12 oe pin names description d 0 ? 7 data inputs cp clock pulse input oe output enable input o 0 ? 7 3-state outputs inputs outputs d n cp oe o n hlh lll xllo 0 xxhz logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. cp o 0 cp oe o 1 o 2 o 3 o 4 o 5 o 6 o 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d o cp d o cp d o cp d o cp d o cp d o cp d o cp d o
3 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs absolute maximum ratings the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values de?ed in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ?ecommended operating conditions table will de?e the conditions for actual device operation. recommended operating conditions 5 notes: 4. i o absolute maximum rating must be observed. 5. unused inputs or i/os must be held high or low. they may not float. symbol parameter conditions value units v cc supply voltage ? 0.5 to + 7.0 v v i dc input voltage ? 0.5 to + 7.0 v v o dc output voltage output in 3-state ? 0.5 to + 7.0 v output in high or low state 4 ? 0.5 to v cc + 0.5 i ik dc input diode current v i < gnd ? 50 ma i ok dc output diode current v o < gnd ? 50 ma v o > v cc + 50 i o dc output source/sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature ? 65 to + 150 c symbol parameter conditions min. max. units v cc supply voltage operating 2.0 3.6 v data retention 1.5 3.6 v i input voltage 0 5.5 v v o output voltage high or low state 0 v cc v 3-state 0 5.5 i oh / i ol output current v cc = 3.0v ? 3.6v 24 ma v cc = 2.7v ? 3.0v 12 v cc = 2.3v ? 2.7v 8 t a f ree-air operating temperature ? 40 85 c ? t / ? v input edge rate v in = 0.8v ? 2.0v, v cc = 3.0v 0 10 ns / v
4 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs dc electrical characteristics ac electrical characteristics notes: 6. outputs disabled or 3-state only. 7. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to- high (t oslh ). symbol parameter conditions v cc (v) t a = ? 40 c to + 85 c units min. max. v ih high level input voltage 2.3 ? 2.7 1.7 v 2.7 ? 3.6 2.0 v il low level input voltage 2.3 ? 2.7 0.7 v 2.7 ? 3.6 0.8 v oh high level output v oltage i oh = ? 100 a 2.3 ? 3.6 v cc ? 0.2 v i oh = ? 8ma 2.3 1.8 i oh = ? 12ma 2.7 2.2 i oh = ? 18ma 3.0 2.4 i oh = ? 24ma 3.0 2.2 v ol low level output v oltage i ol = 100 a 2.3 ? 3.6 0.2 v i ol = 8ma 2.3 0.6 i ol = 12ma 2.7 0.4 i ol = 16ma 3.0 0.4 i ol = 24ma 3.0 0.55 i i input leakage current 0 v i 5.5v 2.3 ? 3.6 5.0 a i oz 3-state output leakage 0 v o 5.5v, v i = v ih or v il 2.3 ? 3.6 5.0 a i off po w er-off leakage current v i or v o = 5.5v 0 10 a i cc quiescent supply current v i = v cc or gnd 2.3 ? 3.6 10 a 3.6v v i , v o 5.5v 6 2.3 ? 3.6 10 ? i cc increase in i cc per input v ih = v cc ? 0.6v 2.3 ? 3.6 500 a symbol parameter t a = ? 40 c to + 85 c, r l = 500 ? units v cc = 3.3v 0.3v v cc = 2.7v v cc = 2.5 0.2 c l = 50pf c l = 50pf c l = 30pf min. max. min. max. min. max. f max maximum clock frequency 150 150 150 mhz t phl , t plh propagation delay cp to o n 1.5 8.5 1.5 9.5 1.5 10.5 ns t pzl , t pzh output enable time 1.5 8.5 1.5 9.5 1.5 10.5 ns t plz , t phz output disable time 1.5 7.5 1.5 8.5 1.5 9.0 ns t s setup time 2.5 2.5 4.0 ns t h hold time 1.5 1.5 2.0 ns t w pulse width 3.3 3.3 4.0 ns t oshl , t oslh output to output skew 7 1.0 ns
5 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs dynamic switching characteristics capacitance symbol parameter conditions v cc (v) t a = 25 c units t ypical v olp quiet output dynamic peak v ol c l = 50pf, v ih = 3.3v, v il = 0v 3.3 0.8 v c l = 30pf, v ih = 2.5v, v il = 0v 2.5 0.6 v olv quiet output dynamic valley v ol c l = 50pf, v ih = 3.3v, v il = 0v 3.3 ? 0.8 v c l = 30pf, v ih = 2.5v, v il = 0v 2.5 ? 0.6 symbol parameter conditions typical units c in input capacitance v cc = open, v i = 0v or v cc 7pf c out output capacitance v cc = 3.3v, v i = 0v or v cc 8pf c pd po w er dissipation capacitance v cc = 3.3v, v i = 0v or v cc , f = 10 mhz 25 pf
6 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs ac loading and waveforms (generic for lcx family) figure 1. ac test circuit (c l includes probe and jig capacitance) t est switch t plh , t phl open t pzl , t plz 6v at v cc = 3.3 0.3v v cc x 2 at v cc = 2.5 0.2v t pzh , t phz gnd v cc dut c l 500 ? 500 ? open t plh , t phl t pzh , t phz t pzl , t plz gnd v i test signal wa veform for inverting and non-inverting functions propagation delay. pulse width and t rec wa veforms 3-state output low enable and disable times for logic 3-state output high enable and disable times for logic setup time, hold time and recovery time for logic t rise and t fall v cc gnd d ata in d ata out t pxx t pxx v mi v mo v cc gnd control in clock output t phl t plh t rec t w v mi v mi v mo v mo v cc v x v ol gnd d ata out output control t pzl t plz v mi v mo d ata out output control t pzh t phz v cc gnd v mi v oh v y v mo d ata in control input mr or clear t s t s t h t rec v cc gnd v cc gnd v mi v mi v mi any output t r t f v oh v ol 10% 10% 90% 90% figure 2. waveforms (input characteristics; f =1mhz, t r = t f = 3ns) symbol v cc 3.3v 0.3v 2.7v 2.5v 0.2v v mi 1.5v 1.5v v cc / 2 v mo 1.5v 1.5v v cc / 2 v x v ol + 0.3v v ol + 0.3v v ol + 0.15v v y v oh ? 0.3v v oh ? 0.3v v oh ? 0.15v
7 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs schematic diagram (generic for lcx family) esd esd input stage output input stage p1 p2 p5 x1 gto v cc v dd n1 n+/p d2 p3 p4 n4 n5 n3 n+/p d4 n+/p d6 data enable n2
8 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs t ape and reel speci?ation t ape format for dqfn t ape dimensions inches (millimeters) reel dimensions inches (millimeters) package designator t ape section number cavities cavity status cover tape status bqx leader (start end) 125 (typ) empty sealed carrier 3000 filled sealed tr ailer (hub end) 75 (typ) empty sealed t ape size abcdnw1w2 12 mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4)
9 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m20b
10 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs physical dimensions (continued) inches (millimeters) unless otherwise noted pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
11 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs physical dimensions (continued) inches (millimeters) unless otherwise noted pb-free 20-terminal depopulated quad very-thin flat pack no leads (dqfn), jedec mo-241, 2.5 x 4.5mm package number mlp020b
12 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs physical dimensions (continued) inches (millimeters) unless otherwise noted 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide package number msa20
13 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs physical dimensions (continued) inches (millimeters) unless otherwise noted 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20
14 www.fairchildsemi.com 74lcx374 rev. 2.0.0 74lcx374 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fa irchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production isoplanar littlefet microcoupler microfet micropak microwire msx msxpro ocx ocxpro optologic optoplanar p acman pop power247 poweredge f ast f astr fps frfet globaloptoisolator gto hisec i 2 c i-lo implieddisconnect intellimax rev. i18 acex activearray bottomless build it now coolfet crossvolt dome ecospark e 2 cmos ensigna f act f act quiet series powersaver powertrench qfet qs qt optoelectronics quiet series rapidconfigure rapidconnect serdes scalarpump silent switcher smart start spm ste alth superfet supersot-3 supersot-6 supersot-8 syncfet tcm tinylogic tinyopto trutranslation uhc ultrafet unifet vcx wire across the board. around the world. the power franchise programmable active droop

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